SIP Packaging Process Flow

System-in-package (SIP) technology has been widely accepted by academia and industry since it was proposed in the early 90s of the 20th century, and has become a new focus of electronic technology research and one of the main directions of technology application, and is regarded as representing the future development direction of electronic technology. As an important part of SIP packaging technology, SIP packaging process has made significant progress in continuous innovation in recent years, and has gradually built its own technical system, which is worthy of research and exploration by technicians and scholars in related technology industries. From the perspective of packaging process, this paper comprehensively expounds the SIP packaging manufacturing and analyzes its process points in detail.

1.引言：The existing commercial components are used, and the manufacturing cost is low; System-in-package (SIP) refers to the use of different technologies to mix different types of components in the same package to form a system-integrated package. This definition has evolved gradually. At first, passive components were added to a single-chip package (at this time, the package form was mostly QFP, SOP, etc.), and then it developed into adding multiple chips, laminated chips, and passive devices to a single package, and finally evolved into a package to form a system (at this time, the package form was mostly BGA and CSP). SIP is the product of the further development of multi-chip packaging (MCP), the difference between the two is that SIP can carry different types of chips, and the chips can access and exchange signals between them, and then have a certain function at the scale of a system; The multiple chips stacked in MCP are usually of the same type, and the memory that cannot be accessed and exchanged between chips is the mainstay, and it is generally a multi-chip memory. - Lower manufacturing costs due to the use of existing commercial components; - Greater flexibility in design and process;

2. Overview of SIP packaging: - Greater flexibility in design and process; System-in-package (SIP) technology has been widely accepted by academia and industry since it was proposed in the early 90s of the 20th century, and has been widely accepted by academia and industry after more than ten years of development, becoming a new hot spot in electronic technology research and one of the main directions of technology application, and is considered to represent one of the development directions of future electronic technology.

1. Wire bonding packaging process

There are usually two ways to realize the function of the electronic system: one is the system-on-chip (SOC), that is, to realize the function of the electronic system on a single chip; The other is system-in-package (SIP), which implements the functions of the whole system through packaging. From an academic point of view, these are two technical routes, just like monolithic integrated circuits and hybrid integrated circuits, each with its own advantages and application markets, and it is complementary to each other in terms of technology and application. From a product perspective, SOC is mainly used for high-performance products with a long cycle, while SIP is mainly used for consumer products with a short cycle. SIP uses mature assembly and interconnection technology to integrate various integrated circuits such as CMOS circuits, GaAs circuits, SiGe circuits, optoelectronic devices, MEMS devices, capacitors, inductors and other passive components into a package to realize the function of the whole system. Its main advantages are as follows: system-in-package (SIP) technology has been widely accepted by academia and industry after decades of development since the early 90s of the 20th century, and has become one of the new hot spots and main directions of technical application in electronic technology research, and is considered to represent one of the directions of electronic technology development in the future. According to the design type and structure of SIP in the current industry, SIP can be divided into three categories.

2. Wire bonding

- Short time-to-market for products; Stacked SIP is a package that uses a physical method to physically stack two or more chips in a package to package it. One of the important roles of cleaning is to improve the adhesion of the membrane, such as depositing the Au film on the Si substrate and treating the surface of hydrocarbons and other contaminants with Ar plasma, which significantly improves the adhesion of the Au. After plasma treatment, the surface of the substrate will leave a layer of fluoride-containing gray substance, which can be removed with a solution. At the same time, cleaning also helps to improve surface adhesion and wettability.

- Greater flexibility in design and process; 3.3 3D SIP is a package based on 2D packaging, which interconnects multiple bare chips, packaging chips, multiple chips and even wafers in stacks to form a three-dimensional package, which is also known as stacked 3D packaging. At present, there are two types of ball planting methods used in the industry: "焊膏" + "solder balls" and "通量 paste" + "solder balls". "Solder paste" + "solder ball" ball planting method is recognized as the best standard ball planting method in the industry, the ball implanted by this method has good weldability and good luster, and the solder ball bias phenomenon will not occur in the tin melting process, which is easier to control, the specific method is to print the solder paste on the pad of BGA first, and then use the ball planting machine or screen printing to add a certain size of solder ball on it, at this time, the role of the solder paste is to stick to the solder ball, and make the contact surface of the solder ball larger when heating, so that the heating of the solder ball is faster and more comprehensive. It makes the solder ball weldable to the pad better after soldering and reduces the possibility of virtual soldering.

- Integrating different types of circuits and components together is relatively easy to implement.

3. SIP packaging process: According to the connection between the chip and the substrate, the SIP packaging process can be divided into two types: wire bonding packaging and flip soldering. In order to improve productivity and conserve materials, most SIP assembly is performed in an array combination, which is divided into individual parts after the molding and testing process is completed. The division can be sawed or stamped process, the sawing process is more flexible, and does not require many special tools, and the stamping process has higher production efficiency and lower cost, but requires the use of special tools.

System-in-package (SIP) technology has been widely accepted by academia and industry since it was proposed in the early 90s of the 20th century, and has become a new hotspot in electronic technology research and one of the main directions of technology application, and is considered to represent one of the development directions of future electronic technology.

1. Wire bonding packaging process: wafer → wafer thinning→ wafer cutting→ die bonding→ wire bonding→ plasma cleaning→ liquid sealant, potting→ assembly, solder, ball →, reflow soldering→, surface marking→ separation, final inspection→ testing→ packaging → final inspection testing packaging.

2. It provides more convenience for electronic designers in the design of the power supply/ground distribution of the chip; In terms of process, there are two processes in SIP packaging: wire bonding packaging and flip soldering. Wire bonding packaging involves a series of processes, from wafer handling to final packaging, each of which has its own technical points, such as die downgauging to meet die assembly requirements, lead specifications, and bonding technology. The flip soldering process overcomes some of the problems of wire bonding and has many advantages, such as overcoming the pad center distance limit, providing more design convenience, improved signal transmission, excellent thermal performance, and high reliability.

However, SIP also has technical difficulties. In circuit design, 3D chip packaging involves multi-die stacking, which will bring problems such as chip stacking methods, multi-layer substrate routing, trace spacing, and equal length and differential pair design.

4. SIP Package Type:

1. Disc thinningDisc thinning refers to the use of mechanical or chemical mechanical (CMP) grinding from the back of the disc to reduce the disc to the extent that it is suitable for packaging. Due to the increasing size of the disc, the thickness of the discs has been increasing in order to increase the mechanical strength of the discs and prevent deformation and cracking during processing. However, as the system moves towards thinness and shortness, the thickness of the module becomes thinner after chip packaging, so the thickness of the disc must be reduced to an acceptable degree before packaging to meet the requirements of the chip assembly.

According to the design type and structure of SIP in the current industry, SIP can be divided into three categories. Disc cutting, disc thinning can be diced. Older dicing machines were manually operated, while most dicing machines are now fully automated. Whether it is partially scribing or completely splitting the wafer, a saw knife is now used because it creates neat edges and few chips and tears.

SIP4.1.3 Die Bonding Chips that have been cut are placed on the middle pads of the frame. The pad size needs to match the chip size, if the pad size is too large, it will cause the lead span to be too large, and the lead wire will be bent and the chip will be displaced due to the stress generated by the flow during the transfer molding process. The placement method can be soldered to the substrate with soft solder (Pb-Sn alloy, especially Ann-containing alloys), Au-Si eutectic alloy, etc., and the most common method in plastic packaging is to use a polymer binder to paste to the metal frame.

5. The substrate of the package

1. This kind of packaging is to arrange the chips one by one in a two-dimensional mode on the same packaging substrate and package it in a package. The lead wires used in plastic packaging for wire bonding are mainly gold wires, which are generally 0.025mm - 0.032mm in diameter, and the lead length is often between 1.5mm - 3mm, while the height of the arc ring can be 0.75mm higher than the plane where the chip is located. In terms of structure, substrate materials can be divided into two categories: rigid substrate materials and flexible substrate materials. Rigid substrate materials are widely used, and the general rigid substrate materials are mainly copper clad laminates. It is made of reinforcing material, impregnated with resin adhesive, dried, cut, and stacked into a blank, and then covered with a layer of pure copper foil with high conductivity and good weldability, and used as a mold with steel plate to be processed by high temperature and high pressure molding in a hot press.

2. Stacked SIP bonding technology includes hot pressure welding, thermoultrasonic welding, etc. The advantages of these techniques are the ease with the formation of spherical shapes (i.e., solder ball technology) and the ability to prevent oxidation of the gold wires. In order to reduce costs, other metal wires such as aluminum, copper, silver, and palladium are also being studied to replace gold wire bonding. The condition of hot pressure welding is that the surfaces of two metals are in close contact, and the two metals are joined by controlling time, temperature, and pressure. Rough (uneven) surfaces, the formation of oxide layers, chemical contamination, moisture absorption, etc., will affect the bonding effect and reduce the bonding strength. The temperature of hot pressure welding is between 300°C - 400°C, and the time is generally 40ms (usually, with procedures such as finding the bond position, the bonding speed is two wires per second). The advantage of ultrasonic welding is that it can avoid high temperatures, because it uses ultrasonic vibration of 20kHz - 60kHz to provide the energy required for welding, so the welding temperature can be reduced somewhat. The use of both thermal and ultrasonic energy for bonding is known as thermoultrasonic welding. Compared with hot pressure welding, the biggest advantage of thermosonic welding is that the bonding temperature is reduced from 350°C to about 250°C (some people think that 100°C - 150°C conditions can be used), which can greatly reduce the possibility of Au-Al intermetallic compounds forming on aluminum pads, prolong the life of the device, and reduce the drift of circuit parameters. Improvements in wire bonding are mainly due to the need for thinner and thinner packages, some of which are only about 0.4mm thick. Therefore, the lead loop is reduced from the general 200mm - 300mm to 100mm - 125mm, so that the lead tension is very large and very tight. In addition, there are usually two ring-shaped power/ground wires on the periphery of the lead pad on the substrate, and the minimum gap between the gold wire and the wire must be > 625 mm to prevent short circuit with it during bonding, and the bond lead must have high linearity and good arc shape.

3. The manufacturing process of the packaging substrate

This type of packaging is a package that physically combines two or more chips on top of each other in a single package. An important effect of cleaning is to improve the adhesion of the film, for example, when depositing Au film on Si substrate, the adhesion of Au can be significantly improved after the surface of hydrocarbons and other contaminants is treated by Ar plasma. The surface of the plasma-treated matrix leaves a layer of fluoride-containing grey substance, which can be removed with a solution. At the same time, cleaning also helps to improve surface adhesion and wettability. As a precious metal, gold has the advantages of good solderability, oxidation resistance, corrosion resistance, small contact resistance, and good alloy wear resistance

4. 3D SIP places the die-mounted and wire-bonded frame tape in a mold, heats the preforming blocks of the mold compound in a preheating oven (preheating temperature between 90°C and 95°C) and places them in the transfer tank of the transfer molding machine. Under the pressure of the transfer piston, the mold compound is extruded into the sprue and injected into the mold cavity through the gate (the mold temperature is maintained at around 170°C - 175°C throughout the process). The molding material is quickly cured in the mold, and after a period of pressure holding, the module reaches a certain hardness, and then the module is ejected with a push rod, and the molding process is completed. For most molding compounds, after a few minutes of holding pressure in the mold, the module is hard enough to allow ejection, but the curing (polymerization) of the polymer is not complete. Because the degree of polymerization (degree of curing) of the material strongly affects the glass transition temperature and thermal stress of the material, it is very important to promote the curing of the material to achieve a stable state, which is very important to improve the reliability of the device, and the post-curing is a necessary process step to improve the polymerization degree of the molding material, and the general post-curing conditions are 170 °C - 175 °C, 2h - 4h.

Assembling solder ball plating refers to the electrolytic reaction in solution with the help of external direct current, which is the surface of a conductor (such as metal) to take advantage of the metal or alloy layer. Electroplating is divided into electroplating hard gold and soft gold process, the process of plating hard gold and soft gold is basically the same, the composition of the tank liquid is basically the same, the difference is that some trace metal nickel or cobalt or iron and other elements are added to the hard gold tank, because the thickness and composition of the plated metal in the electroplating process are easy to control, and the flatness is excellent, so when the surface treatment of the packaging substrate using the bonding process is carried out, the electroplated nickel gold process is generally used, the bonding of aluminum wire is generally made of hard gold, and the bonding of gold wire is generally made of soft gold. Whether it is electroless nickel gold or electroplated nickel gold, the key to the bond quality is whether the crystallization of the plating and the surface are contaminated, as well as the required nickel gold thickness.

5. This kind of packaging is based on 2D packaging, and multiple bare chips, packaging chips, multiple chips and even discs are interconnected in a stack to form a three-dimensional package, which is also called a stacked 3D package. At present, there are two kinds of ball planting methods used in the industry: "solder paste" + "solder ball" and "flux paste" + "solder ball". "左侧粘贴" + "solder ball" balling method is recognized as the best standard ball planting method in the industry, the ball implanted by this method has good weldability and good luster, and the solder ball bias phenomenon will not occur in the tin melting process, which is easier to control, the specific method is to print the 焊膏 on the pad of BGA first, and then use the ball planting machine or screen printing to add a certain size of solder ball on it, then the solder paste plays the role of sticking to the solder ball, and makes the contact surface of the solder ball larger when heating, so that the solder ball is heated faster and more comprehensively. It makes the solder ball weldable to the pad better after soldering and reduces the possibility of virtual soldering. SiP is a combination of a variety of functional chips, including processors, memories and other functional chips in a package, so as to achieve a basically complete function. Corresponding to SOC (System on Chip). The difference is that system-in-package is a packaging method that uses different chips side-by-side or superimposed, while SOC is a highly integrated chip product.

6. The process technology of SIP packaging: marking is to print letters and logos that are not easy to erase and clear handwriting on the top surface of the packaging module, including the manufacturer's information, country, device code, etc., mainly for identification and tracking. There are many methods of coding, the most commonly used of which is the printing method, and it includes ink printing and laser printing.

6. More Moore VS More than Moore - Comparison between SoC and SiP SiP is an important implementation path beyond Moore's law. The well-known Moore's Law has developed to the present stage, where is it going? There are two paths in the industry: one is to continue to develop according to Moore's Law, and the products that take this path are CPU, memory, logic devices, etc., which account for 50% of the entire market. In addition, the More than Moore route that surpasses Moore's Law, the development of chips has shifted from blindly pursuing power consumption reduction and performance improvement to meeting the needs of the market more pragmatically. These products include analog/RF devices, passive components, power management devices, etc., which account for about the remaining 50% of the market.

SiP is an important implementation path beyond Moore's Law. Moore's Law has developed so far, and the subsequent direction is a mystery. There are two paths in the industry: one is to continue to follow Moore's Law, and products such as CPUs, memory, and logic devices take this path, which accounts for 50% of the entire market. The second is the More than Moore route that surpasses Moore's Law, and the development of chips has shifted from simply pursuing power consumption reduction and performance improvement to being more in line with market demand. Products in this area include analog/RF devices, passive components, power management devices, etc., accounting for about the remaining 50% of the market share. SoCs are very similar to SIPs, both of which combine a system with logical components, memory components, and even passive components in a single unit. From a design point of view, an SoC is a highly integrated system with the components required by the system onto a single chip. SiP is a single standard package that combines multiple active electronic components with different functions with optional passive components and other devices such as MEMS or optics from a packaging standpoint by placing different chips side-by-side or superimposed.

Based on these two paths, two products have emerged: SoC and SiP. SoC is the product of the continuous development of Moore's Law, and SiP is the key path to achieve beyond Moore's Law. Both aim to achieve miniaturization and miniaturization of systems at the chip level. From the perspective of packaging development, due to the needs of electronic products in terms of volume, processing speed or electrical characteristics, SoC has been established as the key and development direction of future electronic product design. However, in recent years, the production cost of SoC has become higher and higher, and technical obstacles have been frequently encountered, resulting in bottlenecks in the development of SoC, which in turn has made the development of SiP more and more valued by the industry.

SoCs and SIPs are very similar in that they combine a system with logic, memory, and even passive components in a single unit. From a design perspective, SoCs are highly integrated into a single chip with the components required for the system. From the perspective of packaging, SiP adopts the packaging method of side-by-side or superposition of different chips, and preferentially assembles multiple active electronic components with different functions with optional passive components, as well as other devices such as MEMS or optical devices, so as to achieve a single standard package with certain functions. Moore's Law ensures that chip performance continues to improve. As we all know, Moore's Law is the "bible" for the development of the semiconductor industry. On silicon-based semiconductors, transistors are halved in feature size and performance doubled every 18 months. While the performance is improved, the cost is reduced, which gives semiconductor manufacturers enough incentive to achieve the reduction of semiconductor feature size. Among them, processor chips and memory chips are the two types of chips that most obey Moore's Law. In the case of Intel, each generation of products follows Moore's Law perfectly. At the chip level, Moore's Law drives performance forward.

In terms of integration, in general, SoC only integrates logic systems such as APs, while SiPs integrate AP + mobile DDR, to some extent, SIP = SoC + DDR, and with the increasing integration in the future, eMMC is also very likely to be integrated into SiP. SIP is the winner or loser in solving the shackles of the system. Packaging multiple semiconductor chips and passive components in the same chip to form a system-level chip, instead of using the PCB board as the carrier between the connection of the bearer chip, can solve the problem of system performance bottleneck caused by the inherent deficiency of the PCB itself. In the case of processors and memory chips, the density of internal traces in the SiP can be much higher than that of the PCB, thus solving the system bottleneck caused by the PCB linewidth. For example, because memory chips and processor chips can be connected together through vias, they are no longer limited by the PCB linewidth, so that the data bandwidth can be increased in the interface bandwidth.

From the perspective of packaging development, SoC has been identified as the key and development direction of future electronic product design due to the requirements of electronic products in terms of volume, processing speed or electrical characteristics. However, in recent years, the production cost of SoC has been rising, and technical problems have been frequently encountered, resulting in a bottleneck in the development of SoC, so that the development of SiP has attracted more and more attention from the industry. SiP process analysis

7. SiP - the inevitable choice path beyond Moore's law 2.1. Wire bonding packaging process

Moore's Law ensures that chip performance continues to improve. As we all know, Moore's Law can be called the "bible" for the development of the semiconductor industry. On silicon-based semiconductors, transistor feature sizes are halved every 18 months, doubling performance. The increase in performance has been accompanied by a decrease in cost, which has given semiconductor manufacturers enough incentive to shrink the size of semiconductor features. Among them, processor chips and memory chips are the two types of chips that follow Moore's law the most. Intel, for example, has followed Moore's Law perfectly with each generation of its products. At the chip level, Moore's Law drives performance forward. Wafer → wafer thinning→ wafer cutting→ die bonding→ wire bonding→ plasma cleaning→ liquid sealant, potting→ assembly, solder, ball → reflow soldering→ surface marking→ separation→ final inspection→ testing→ packaging.

The PCB board does not follow Moore's Law, which is the bottleneck of the overall system performance improvement. Contrary to the shrinking size of chips, PCB boards have not changed much over the years. For example, the standard minimum line width for PCB motherboards was 3 mils (about 75 um) ten years ago, and it is still 3 mils today, with little progress. After all, PCBs don't follow Moore's Law. Due to PCB limitations, the performance improvement of the entire system has encountered a bottleneck. For example, since the PCB linewidth does not change, so does the connection density between the processor and the memory. In other words, the number of connections between the processor and memory envelope will not change significantly while the size of the processor and memory package is essentially the same. The memory bandwidth is equal to the memory interface bit width multiplied by the memory interface operation frequency, and the memory output bit width is equal to the number of connections between the processor and the memory, this value is limited by the PCB board process, and has been 64bit for ten years, so to increase the memory bandwidth can only increase the memory interface operation frequency, which limits the performance improvement of the entire system. Disc thinning refers to the mechanical or chemical mechanical (CMP) grinding from the back of the disc to the extent that it is suitable for packaging. As the size of the disc is getting larger and larger, the thickness of the disc is increasing in order to increase the mechanical strength of the disc and prevent deformation and cracking during processing. However, as the system develops in the direction of lightness, thinness and shortness, the thickness of the module becomes thinner and thinner after chip packaging, so the thickness of the disc must be reduced to an acceptable degree before packaging to meet the requirements of chip assembly.

SIP is the key to solving system constraints. Packaging multiple semiconductor chips and passive components in the same chip to form a system-on-chip, no longer using the PCB board as the carrier to carry the chip connection, can solve the problem of system performance bottleneck caused by PCB's own defects. Taking processors and memory chips as examples, the internal trace density of the system-in-package is much higher than that of the PCB, which can solve the system bottleneck caused by the PCB line width. For example, memory chips and processor chips can be connected through vias, which are no longer limited by the PCB linewidth, so that the data bandwidth can be increased in the interface bandwidth. After the disc is thinned, it can be diced. Older dicing machines were manually operated, while most dicing machines are now fully automated. Whether it is partially scribing or completely splitting the wafer, a saw knife is now used because it has neat edges and few chips and tears.

We believe that SiP is more than simply integrating chips together. SiP also has the advantages of short development cycle, more functions, lower power consumption, better performance, lower cost, smaller size, and lighter weight, which can be summarized as follows: the cut chip is placed on the middle pad of the frame. The size of the pad should match the size of the chip, if the size of the pad is too large, it will cause the lead span to be too large, and the lead will be bent and the chip will be displaced due to the stress generated by the flow during the transfer molding process. Placement can be done by soldering to the substrate with soft solder (Pb-Sn alloys, especially those containing Sn), Au-Si eutectic alloys, etc., and the most common method in plastic packaging is to use a polymer binder to attach to a metal frame.

8. SiP process analysis

The lead wire used in plastic packaging is mainly gold wire, and its diameter is generally 0.025mm~0.032mm. The length of the lead wire is usually between 1.5mm~3mm, and the height of the arc circle can be 0.75mm higher than the plane where the chip is located.

• The SIP packaging process can be divided into two types: wire bonding packaging and flip soldering according to the connection between the chip and the substrate. Plasma cleaning

• 2.1. Wire bonding encapsulation process: liquid sealant potting

• The main process of wire bonding encapsulation process is as follows: liquid sealant potting

• Wafer → wafer thinning→ wafer cutting→ die bonding→ wire bonding→ plasma cleaning→ liquid sealant potting→ assembly, solder, ball → reflow soldering→ surface marking→ separation→ final inspection→ testing→ packaging. Surface marking

• Disc thinning separation

Disc thinning refers to the mechanical or chemical mechanical (CMP) grinding from the back of the disc to the extent that the disc is suitable for packaging. With the increase of the size of the disc, in order to increase the mechanical strength of the disc, prevent deformation and cracking during processing, its thickness increases. However, as the system develops in the direction of lightness, thinness and shortness, the thickness of the module after chip packaging is getting thinner and thinner, so the thickness of the disc must be reduced to an acceptable degree before packaging to meet the requirements of chip assembly. 2.2. Flip welding process

Disc cutting (1) flip welding technology overcomes the problem of the center distance limit of wire bonding pads;

The disc can be diced after thinning. The old dicing machine was manually operated, but now the general dicing machine is fully automated. Saws are now used for both partial and complete scribing of wafers, as they have neat edges and few chips and tears. (3) By shortening the interconnection length and reducing the RC delay, it provides a more complete signal for high-frequency and high-power devices;

Die bonding (5) has high reliability, and the anti-fatigue life of the package is enhanced due to the effect of the under-chip filler;

The cut die is placed on the pad in the middle of the frame. The pad size needs to match the chip size, if the pad size is too large, it will cause the lead span to be too large, and the stress generated by the flow will cause the lead to bending and chip displacement during the transfer molding process. The mounting method can be soldered to the substrate with soft solder (such as Pb-Sn alloy, especially Sn-containing alloys), Au-Si eutectic alloy, etc., and the most common method in plastic packaging is to paste a polymer binder to a metal frame. The following is the process of flip soldering (the same process parts as wire bonding are not separately described): disc → pad redistribution→ disc thinning, bumping → disc cutting→ flip bonding, underfilling→ encapsulation→ assembling solder balls→ reflow soldering→ surface marking→ separation→ final inspection→ testing → packaging.

Wire bondingIn order to increase the lead spacing and meet the requirements of the flip soldering process, wire bonding requires redistribution of the lead wires of the chip.

Most of the leads used in plastic packaging are gold wires, with a diameter of 0.025mm - 0.032mm, a lead length of 1.5mm - 3mm, and a curved circle height of 0.75mm higher than the plane where the chip is located. After the pad redistribution is completed, it is necessary to add bumps to the pads on the chip, and the solder bump manufacturing technology can be electroplating, electroless plating, evaporation, ball placement and solder paste printing. At present, electroplating is still the most widely used, followed by 焊膏printing.

Bonding technologies include hot pressure welding, thermosonic welding, etc. The advantages of these techniques are that they are easy to form spherical (i.e., solder ball technology) and prevent oxidation of the gold wires. In order to reduce costs, we are also studying the use of metal wires such as aluminum, copper, silver, and palladium to replace gold wire bonding. Thermostatic welding requires the two metal surfaces to be in close contact, and the two metals are joined by controlling time, temperature, and pressure. Rough (uneven) surfaces, the formation of oxide layers, chemical contamination, moisture absorption, etc., will affect the bonding effect and reduce the bonding strength. The hot pressure soldering temperature is 300°C - 400°C, and the time is generally 40ms (usually, with the procedure of finding the bond position, etc., the bonding speed is two wires per second). The advantage of ultrasonic welding is that it avoids high temperatures, and it uses ultrasonic vibration from 20kHz to 60kHz to provide the energy required for welding, thus reducing the welding temperature. The use of both thermal and ultrasonic energy for bonding is known as thermoultrasonic welding. Compared with thermo-pressure welding, the biggest advantage of thermosonic welding is that the bonding temperature is reduced from 350°C to about 250°C (some people believe that 100°C - 150°C conditions can be used), which can greatly reduce the possibility of Au-Al intermetallic compounds forming on aluminum pads, prolong the device life, and reduce circuit parameter drift. Improvements in wire bonding stem from the need for thinner and thinner packages, some of which are only about 0.4mm thick. Therefore, the lead loop is reduced from the general 200mm - 300mm to 100mm - 125mm, so that the lead tension increases and is very tight. In addition, there are usually two ring-shaped power/ground wires on the periphery of the lead pad on the substrate, and the minimum gap between the bond wire and the gold wire must be > 625 mm to prevent short circuits during bonding, which requires high linearity and good arc shape of the bond lead. After the solder bumps are arranged in the shape of a grid array on the entire chip bonding surface, the chip is mounted on the package substrate in an inverted manner, and the bumps are electrically connected to the pads on the substrate, replacing the connection method of WB and TAB with terminals arranged around the perimeter. After flip bonding, epoxy resin is used to fill the chip and substrate, which reduces the thermal and mechanical stress applied to the bumps, and improves reliability by 1 to 2 orders of magnitude compared to no filling.

9. One of the important roles of plasma cleaning is to improve the adhesion of the membrane, for example, the adhesion of Au is significantly improved after the deposition of Au film on Si substrate and the treatment of hydrocarbons and other pollutants on the surface by Ar plasma. The surface of the plasma-treated matrix leaves a layer of fluoride-containing grey substance, which can be removed with a solution. At the same time, cleaning also helps to improve surface adhesion and wettability. The most widely used wireless communication field. SiP is the earliest and most widely used in the field of wireless communication. In the field of wireless communication, the requirements for functional transmission efficiency, noise, volume, weight and cost are getting higher and higher, forcing wireless communication to develop in the direction of low cost, portability, multi-function and high performance. SiP is the ideal solution that combines the advantages of existing core resources and semiconductor production processes to reduce costs and time-to-market, while overcoming the challenges of SOC such as process compatibility, signal mixing, noise interference, and electromagnetic interference. The RF power amplifier in the mobile phone integrates the functions of frequency power amplifier, power control and transceiver transfer switch, which is completely solved in SiP.

Liquid sealant potting medical electronics requires a combination of reliability and small size, while combining functionality and longevity. Typical applications in this area are implantable electromedical devices, such as capsule endoscopes. The endoscope is composed of an optical lens, an image processing chip, a radio frequency signal transmitter, an antenna, a battery, etc. Among them, the image processing chip is a digital chip, the RF signal transmitter is an analog chip, and the antenna is a passive device. Centralizing these devices within a single SiP perfectly addresses the performance and miniaturization requirements.

The die-mounted and wire-bonded frame tape is placed in a mold, the preforming blocks of the molding compound are heated in a preheating furnace (preheating temperature between 90°C and 95°C) and placed in the transfer tank of the transfer molding machine. Under the pressure of the transfer forming piston, the mold compound is extruded into the sprue and injected into the mold cavity through the gate (the mold temperature is maintained at around 170°C - 175°C throughout the process). The molding material is quickly cured in the mold, and after a period of pressure, the module reaches a certain hardness, and then the module is ejected with a push rod, and the molding process is completed. For most molding compounds, after a few minutes of holding pressure in the mold, the module is hard enough to allow ejection, but the curing (polymerization) of the polymer is not complete. Because the degree of polymerization (degree of curing) of the material strongly affects the glass transition temperature and thermal stress of the material, it is very important to promote the curing of the material to achieve a stable state to improve the reliability of the device, and the post-curing is a necessary process step to improve the polymerization degree of the molding material, and the general post-curing conditions are 170°C - 175°C, 2h - 4h. SiP also has many applications in other consumer electronics. This includes ISP (image processing chip), Bluetooth chip, etc. ISP is the core device of digital cameras, scanners, cameras, toys and other electronic products, which converts optical signals into digital signals through photoelectric conversion, and then realizes image processing, display and storage. Image sensors include a range of different types of components, such as CCDs, COMS image sensors, contact image sensors, charge-loading devices, optical diode arrays, amorphous silicon sensors, etc., SiP technology is undoubtedly an ideal packaging technology solution.

Liquid sealant potting military electronic products have the characteristics of high performance, miniaturization, multi-variety and small batch, SiP technology conforms to the application needs of military electronics, so it has a wide range of application markets and development prospects in this technical field. SiP products involve satellites, launch vehicles, aircraft, missiles, radars, supercomputers and other military equipment, and the most typical application products are transceiver components of various frequency bands.

At present, there are two kinds of ball planting methods used in the industry: "solder paste" + "solder ball" and "通量 paste" + "solder ball". The "焊膏" + "solder ball" balling method is recognized as the best standard balling method in the industry, and the balls planted in this method have good weldability and good luster, and the solder ball bias will not occur in the tin melting process, which is easy to control. The specific method is to print the solder paste on the pad of BGA first, and then add a certain size of solder ball with a ball planting machine or screen printing, at this time, the solder paste plays the role of sticking to the solder ball, and when heating, the contact surface of the solder ball is larger, so that the solder ball is heated faster and more comprehensively, so that the solder ball and the pad have better weldability after melting and reduce the possibility of virtual soldering. The thinness of mobile phones has led to an increase in demand for SiP. Mobile phones are the largest market for SiP packaging. As smartphones become thinner and lighter, the demand for SiP is naturally rising. From 2011 to 2015, the thickness of mobile phones of various brands has been shrinking. Thinning naturally places higher and higher demands on the thickness of assembled parts. Taking the iPhone 6s as an example, the use of PCB has been greatly reduced, and many chip components will be in the SiP module, and the iPhone 8 may be Apple's first mobile phone to use SiP in the whole machine. This means that the iPhone 8 can be made thinner and lighter, and on the other hand, there will be more space for other functional modules, such as a more powerful camera, speakers, and battery.

In addition to watches, the number of SiP used in Apple mobile phones is also gradually increasing. The list includes: touch chip, fingerprint recognition chip, RFPA, etc.

Marking is to print letters and logos on the top surface of the package module with clear handwriting, including manufacturer information, country, device code, etc., which are mainly used for identification and tracking. There are many coding methods, the most commonly used of which is the printing method, which includes ink printing and laser printing. Fingerprint recognition is also available in a SiP package. Sensors and control chips are packaged together, starting with the iPhone 5, with similar technology.

According to Apple's habits, all mature technologies will be passed on to the next generation, and we judge that the upcoming Apple iPhone7 will adopt more SiP technology, while the future iPhone7s and iPhone8 will be more comprehensive and use SiP technology to a greater extent to achieve the compression of internal space.

In order to improve production efficiency and conserve materials, most SIP assembly is carried out in an array combination, which is divided into individual devices after the molding and testing processes are completed. The division and division can be sawed or stamped process, the sawing process is flexible, and does not require too many special tools; The stamping process is highly productive and cost-effective, but requires specialized tools. Since the packaging of integrated circuit devices has entered the integration of multiple components from the development of a single component, it has entered a new stage of packaging integration with the improvement of product efficiency and the demand for lightness, thinness and low consumption. Under the guidance of this development direction, two new mainstreams related to the electronics industry have been formed: System-on-Chip (SoC) and System-in-Package (SIP).

10. Flip soldering process SoC is from the perspective of design, which is to highly integrate the components required by the system into a chip.

Compared to wire bonding, the flip soldering process has the following advantages: the components that make up SIP technology are the packaging carrier and assembly process, which includes PCB, LTCC, Silicon Submount (which can also be an IC in itself), and the assembly process, which includes traditional packaging processes (Wire bond and Flip Chip) and SMT equipment. Passive components are an important part of SIP, such as traditional capacitors, resistors, inductors, etc., some of which can be integrated with the carrier, and others such as inductors and capacitors with high precision, high Q value, and high values are assembled on the carrier through SMT.

(1) Flip welding technology overcomes the problem of the limit of the center distance of the wire bonding pad; From the perspective of packaging development, due to the needs of electronic products in terms of volume, processing speed or electrical characteristics, SoC has been established as the key and development direction of future electronic product design. However, in recent years, as the production cost of SoC has become higher and higher, technical obstacles have been frequently encountered, resulting in bottlenecks in the development of SoC, which in turn has made the development of SIP more and more valued by the industry.

(2) Provide more convenience for electronic designers in the design of the power/ground distribution of the chip; SIP packaging technology uses a variety of bare chips or modules to arrange and assemble, and if the arrangement is differentiated, it can be roughly divided into planar 2D packaging and 3D packaging structure. Compared with 2D packaging, the use of stacked 3D packaging technology can increase the number of wafers or modules used, thereby increasing the number of layers that can be placed in the vertical direction, and further enhancing the functional integration capability of SIP technology. On the other hand, internal bonding technology can be simple wire bonding, flip chip bonding, or a combination of the two.

(3) By shortening the interconnection length and reducing the RC delay, it provides a more complete signal for high-frequency and high-power devices; Technical difficulties of SIP

(4) Excellent thermal performance, heat sink can be installed on the back of the chip; For circuit design, 3D chip packaging will have multiple die stacks, and such a complex package design will bring many problems: such as how to stack multiple chips in one package; Another example is that complex wiring requires multi-layer substrates, and it is difficult to lay out the wiring with traditional tools; There are also issues such as spacing between traces, equal length design, differential pair design, etc. 

(5) High reliability, due to the effect of the under-chip filler, the anti-fatigue life of the package is enhanced; SIP has shown unique advantages in meeting the needs of different fields, but it also faces some technical difficulties to overcome.

In terms of application field, SiP is an ideal solution in the field of wireless communication, which overcomes many difficulties of SOC with a variety of advantages, such as the RF power amplifier related functions in mobile phones are completely solved in SiP. In the field of medical electronics, different types of chips, such as capsule endoscopes, are centrally packaged in SiP to meet the performance and miniaturization requirements. In other consumer electronics, such as ISP, Bluetooth chips, etc., SiP is also an ideal packaging technology. Due to the characteristics of military electronic products, SiP technology also has a wide application prospect. From iPhone 6s to iPhone 8, the application of SiP has been deepening, and other such as touch chips, fingerprint recognition chips, etc. are also used in SiP packaging, and this trend will continue to be carried out in future iPhone models.

In terms of process, there are two processes in SIP packaging: wire bonding packaging and flip soldering. Wire bonding packaging involves a series of processes, from wafer handling to final packaging, each of which has its own technical points, such as die downgauging to meet die assembly requirements, lead specifications, and bonding technology. The flip soldering process overcomes some of the problems of wire bonding and has many advantages, such as overcoming the pad center distance limit, providing more design convenience, improved signal transmission, excellent thermal performance, and high reliability.

However, SIP also has technical difficulties. In circuit design, 3D chip packaging involves multi-die stacking, which will bring problems such as chip stacking methods, multi-layer substrate routing, trace spacing, and equal length and differential pair design.

In summary, as an important implementation path beyond Moore's Law, SiP has been widely used in many fields and has a variety of advantages, but it also faces some technical challenges that need to be continuously solved and optimized in the development process.

SIP has shown unique advantages in meeting the needs of different fields, but it also faces some technical difficulties to overcome.

In terms of application field, SiP is an ideal solution in the field of wireless communication, which overcomes many difficulties of SOC with a variety of advantages, such as the RF power amplifier related functions in mobile phones are completely solved in SiP. In the field of medical electronics, different types of chips, such as capsule endoscopes, are centrally packaged in SiP to meet the performance and miniaturization requirements. In other consumer electronics, such as ISP, Bluetooth chips, etc., SiP is also an ideal packaging technology. Due to the characteristics of military electronic products, SiP technology also has a wide application prospect. From iPhone 6s to iPhone 8, the application of SiP has been deepening, and other such as touch chips, fingerprint recognition chips, etc. are also used in SiP packaging, and this trend will continue to be carried out in future iPhone models.

In summary, as an important implementation path beyond Moore's Law, SiP has been widely used in many fields and has a variety of advantages, but it also faces some technical challenges that need to be continuously solved and optimized in the development process.